As semiconductor processing and fabrication techniques improve, the size of various semiconductor features is reduced. This reduction in size, in turn, allows for the advantageous placement of a greater number of semiconductor devices in a given area. Unfortunately, such reduction in the size of various semiconductor features is not without drawbacks.
One example of a drawback associated with the reduction in size of semiconductor features is found in the area of via inspection. Specifically, as the critical dimension (i.e. the diameter as measured at the bottom of the via) becomes smaller than approximately 0.6 microns, conventional optical inspection is not a feasible method for measuring the critical dimension of the via. Thus, when the critical dimension of a via is less than approximately 0.6 microns a scanning electron microscope examination of the via is required.
With reference now to Prior Art FIG. 1, a side sectional view of a dielectric material 100 having a via 102 formed therein is shown. During a scanning electron microscope examination of via 102, secondary electrons (typically represented by arrows 104 and 106 are generated. Unfortunately, during conventional via examination processes, such secondary electrons 104 and 106 are often absorbed by the material through which the via is formed. As a result, detector 108 does not receive (i.e. detect) secondary electrons 104 and 106. Thus, a conventional scanning electron microscope examination of the via does not always provide an accurate measurement of the via's critical dimension.
As yet another drawback, conventional via examination processes (e.g. optical inspection and scanning electron microscope examination) do not readily provide information on various other parameters of the via being examined. For example, conventional scanning electron microscope examination processes do not readily indicate the depth to which the via has been etched into an underlying material. As a result, in conventional via examination processes, it is not easy to determine if a via extends deep enough into the underlying material. That is, it is difficult to determine if the via "cleared" the depth necessary to ensure that the via opens to the underlying conductive layer. Most commonly, this information is not available until the device is completed and passes electrical tests.
As still another drawback associated with conventional via inspection methods, such prior art approaches do not provide information on the alignment/registration of the via mask. That is, conventional approaches do not readily provide information on the difference between the actual location of a via and the intended location of the via. Therefore, conventional methods require a separate and distinct measurement process to determine the degree of misalignment present in the formation of the vias, or more commonly, the information is not obtained at all.
Thus, a need exists for an apparatus and method for measuring the critical dimension of a via wherein the apparatus and method is feasible even for a via having a critical dimension of less than approximately 0.6 microns. A further need exists for a via formation apparatus and method which readily indicates whether a via has been formed to a desired depth into the underlying dielectric material. Still a further need exists for an apparatus and method which determines the degree of misalignment present in the formation via patterning process.